发明名称 MICROPROCESSOR
摘要 PURPOSE:To improve the processing of a microprocessor by making collectively judgeable the flags of plural arithmetic results only by one instruction. CONSTITUTION:Data are temporarily stored in a temporary register 2 through an internal bus 6, arithmetic logic between the data stored in the register 2 and data stored in an accumulator 1 is executed by an arithmetic unit 3, the logic operation result is stored in the accumulator 1 and a flag flip flop(FF) 4 is set/reset to store flags for one instruction. While shifting a flag in each execution of an arithmetic logic instruction, the flag is inputted to a flag shifting register 5 to store the flags of plural arithmetic logic instructions. The parallel outputs of the register 5 are applied to an arithmetic object in the unit 3 through the bus 6, the flags of plural arithmetic logic instructions are processed by the instructions and the final result is stored in the FF 4.
申请公布号 JPH04294425(A) 申请公布日期 1992.10.19
申请号 JP19910081121 申请日期 1991.03.22
申请人 NEC CORP 发明人 UTSUKI TSUTOMU;IZAWA TOSHIKO
分类号 G06F7/00;G06F9/30 主分类号 G06F7/00
代理机构 代理人
主权项
地址