| 摘要 |
The decoder with simple hardware includes a calculator(44) providing Euclidean distance values(D1-4) calculated from input signal, a hard decision circuit(45) providing most significant 1 bit value (HD1-4) around input value, a matrix calculator(47) providing survival pass and accumulated matric value, a calculator(48) calculating optimal pass in observable region, a pass history calculator(49) providing upper 1 bit directly and lower 1 bit selectively out of 2 bit data input from selected optimal pass to trellis encoder, and a lookup table(50) providing lower 1 bit according selection signal of the pass history calculator.
|
