发明名称 SAR PROVIDED WITH DEDICATED PROCESSING INTERFACE
摘要 <p>PROBLEM TO BE SOLVED: To improve a throughout and to shorten a processing delay time by selecting a processor suitable for processing of a cell from received cells and transmitting information through a dedicated interface. SOLUTION: An ATM cell reception part 101 terminates an ATM cell and writes payload data and associated information to an appropriate frame buffer while checking a header. As soon as information is ready an extraction/judgment/insertion/mediation part 104 activates respective processing engines 200 as needed and respective processing results are reflected on a frame buffer 103. In the processing engine 200, an undefined processing and an exception processing are turned over to a CPU processing, abandoned or detected as an alarm or a fault while cooperating with a mediation control part/CPUIO part/register part 106. A frame for which the proceedings are ended is decomposed into the ATM cells, an ATM layer processing is executed and they are transmitted by an ATM cell transmission part 102.</p>
申请公布号 JPH11205344(A) 申请公布日期 1999.07.30
申请号 JP19980014931 申请日期 1998.01.09
申请人 NEC CORP 发明人 ARAMIZU TATSUO;AMAYA TATSUHIKO;HAMAKAWA YASUHISA;ISOYAMA KAZUHIKO
分类号 H04Q3/00;H04L12/951;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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