发明名称 SEMICONDUCTOR DEVICE HOUSING PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device housing package which is improved in transmission characteristics by reducing the capacitance between line conductors and a ground conductive layer formed on the upper surface of a standing wall. SOLUTION: This semiconductor device housing package includes an input/ output terminal 5 comprising a flat plate 9 consisting of a dielectric having a plurality of line conductors 8 formed extendedly from one side of the upper surface in the direction of the opposed other side, and a standing wall 10 consisting of a dielectric jointed to the upper surface of the flat plate 9 sandwiching a plurality of line conductors 8 therebetween. In this case, the standing wall 10 is jointed to the upper surface of the flat plate 9 through a resin layer 11 of which the dielectric constant is not more than 5 and the porosity is 20-60%.
申请公布号 JP2002329800(A) 申请公布日期 2002.11.15
申请号 JP20010130468 申请日期 2001.04.27
申请人 KYOCERA CORP 发明人 UEDA YOSHIAKI
分类号 H01L23/10;(IPC1-7):H01L23/10 主分类号 H01L23/10
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