发明名称 ELECTRONIC APPLIANCE, AND SEMICONDUCTOR APPARATUS AND FORMATION METHOD THEREFOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a manufacturing process that employs a drop discharge method suitable for a large-sized substrate in terms of volume production considering that a signal delay problem due to the resistance of wiring will possibly become prominent when manufacturing a semiconductor apparatus having a large-area display. <P>SOLUTION: The process includes steps of, forming a foundation layer 11 (or to pre-treat for the foundation layer) beforehand on a substrate that improves its adhesiveness, and forming a mask of a desired pattern shape, which is used to form a desirable concave portion after forming an insulation film. The drop discharge method is used to fill a metal material into the concave portion that has a side wall composed of a mask 13 and the insulation film, thus forming embedded wiring (a gate electrode 15, a power line, guided wiring, and the like). After the mask 13 is removed, planarizing process, such as pressing and CMP, is performed to planarize the element. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005210081(A) 申请公布日期 2005.08.04
申请号 JP20040348620 申请日期 2004.12.01
申请人 SEMICONDUCTOR ENERGY LAB CO LTD 发明人 KUWABARA HIDEAKI;YAMAZAKI SHUNPEI;MAEKAWA SHINJI;NAKAMURA OSAMU
分类号 G02F1/1333;G02F1/1343;G02F1/1368;H01L21/28;H01L21/3205;H01L21/336;H01L23/52;H01L29/423;H01L29/49;H01L29/786;H01L51/50;H05B33/14;(IPC1-7):H01L29/786;H01L21/320;G02F1/136;G02F1/134;G02F1/133 主分类号 G02F1/1333
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