发明名称 Master controller architecture
摘要 A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
申请公布号 US7308633(B2) 申请公布日期 2007.12.11
申请号 US20040999720 申请日期 2004.11.30
申请人 LSI CORPORATION 发明人 ANDREEV ALEXANDRE;GRIBOK SERGEY;BOLOTOV ANATOLI
分类号 G01R31/28;G11C29/00 主分类号 G01R31/28
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