| 摘要 |
The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V 1 than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V 2 than the lower voltage (V 1< V 2<= Vm).
|
