发明名称 Interconnect Structures for Wafer Level Package and Methods of Forming Same
摘要 A method for forming a device package includes forming a molding compound around a plurality of dies and laminating a polymer layer over the dies. A top surface of the dies is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the dies. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of one of the dies.
申请公布号 US2016172329(A1) 申请公布日期 2016.06.16
申请号 US201615052105 申请日期 2016.02.24
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chang Chih-Hao;Chiang Tsung-Hsien;Chen Guan-Yu;Chang Wei Sen;Kuo Tin-Hao;Tsai Hao-Yi;Yu Chen-Hua
分类号 H01L23/00 主分类号 H01L23/00
代理机构 代理人
主权项 1. A device package, comprising: a first die and a second die, a top surface of the first die being vertically offset from a top surface of the second die, relative to a major surface of the first die; a molding compound extending along sidewalls of the first die and the second die, wherein at least a portion of a top surface of the molding compound comprises an inclined surface, the portion of the top surface being between the first die and the second die; a polymer layer contacting the top surface of the molding compound, the top surface of the first die, and the top surface of the second die, wherein a top surface of the polymer layer is substantially level; and a first conductive feature in the polymer layer, wherein the conductive feature is electrically connected to the first die.
地址 Hsin-Chu TW