Clock distribution network for multi-frequency multi-processor systems

摘要

Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.

主权项

1. A method for reconfiguring clock generation circuitry in a clock distribution network of a synchronous digital system, the method comprising:
generating a first clock signal using the clock generation circuitry; selecting the first clock signal as a primary clock for the synchronous digital system, wherein the synchronous digital system is comprised on a chip; detecting a signal indicating possible tampering with the synchronous digital system; selecting a second clock signal as the primary clock in response to the detecting, wherein the second clock signal is generated by an on-chip oscillator that is independent of external clock signals, wherein the selecting the second clock signal comprises causing the second clock signal to replace the first clock signal as the primary clock without causing clock-induced errors in the synchronous digital system; reconfiguring the clock generation circuitry during the time that the second clock signal is acting as the primary clock; and selecting the first clock signal as the primary clock for the synchronous digital system after the clock generation circuitry has stabilized, wherein the selecting the first clock signal comprises causing the first clock signal to replace the second clock signal as the primary clock without causing clock-induced errors in the synchronous digital system.