发明名称 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS
摘要 A precursor comprising a metal 2-ethylhexanoate in a xylenes solvent is applied (P7) to an integrated circuit wafer (1, 20, 50). The wafer is baked (P9) to dry the precursor, annealed (P11) to form a layered superlattice material (12, 30, 60) on the wafer, then the integrated circuit (70) is completed. If the metal is titanium, the precursor comprises titanium 2-methoxyethoxide having at least a portion of its 2-methoxyethoxide ligands replaced by 2-ethylhexanoate. If the metal is a highly electropositive element, the solvent comprises 2-methoxyethanol. If the metal is lead, bismuth, thallium, or antinomy, 1 % to 75 % excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing. The process provides ferroelectric devices having extremely low fatigue and high dielectric constant devices that do not degrade easily.
申请公布号 WO9312538(A1) 申请公布日期 1993.06.24
申请号 WO1992US10542 申请日期 1992.12.08
申请人 SYMETRIX CORPORATION 发明人 PAZ DE ARAUJO, CARLOS, A.;CUCHIARO, JOSEPH, D.;SCOTT, MICHAEL, C.;MCMILLAN, LARRY, D.
分类号 B05D1/00;B05D3/04;B05D7/24;C01G35/00;C23C16/44;C23C16/448;C23C16/455;C23C16/46;C23C16/48;C23C16/52;C23C18/12;C23C26/02;C30B7/00;H01C7/10;H01L21/02;H01L21/314;H01L21/316;H01L21/822;H01L21/8242;H01L21/8246;H01L21/8247;H01L27/04;H01L27/10;H01L27/105;H01L27/108;H01L27/115;H01L29/788;H01L29/792;H01L41/24;H05K3/10 主分类号 B05D1/00
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