发明名称 CLOCK FREQUENCY AND PHASE CORRECTION
摘要 1279106 Automatic phase and frequency control SIERRA RESEARCH CORP 28 Nov 1969 [20 Dec 1968] 58301/69 Heading H3A A synchronizing system of the type in which a clock oscillator 14 to be controlled is compared with a reference clock oscillator to derive "early" and "late" error signals 10b, 10a comprises: "bidirectional means", e.g. up-down counter 24, which produces an output to vary the oscillator frequency in response to a number of consecutive error signals in the same direction; and "intermittent means" e.g. monostables 32, 34 for momentarily shifting the oscillator frequency in response to each early or late signal. The oscillator frequency control signal on line 18 is derived from potentiometers 40 ... 43, 45 ... 48 and triggering the monostables 32, 34 actuates relay 36 or 38 to shift this control signal in a sense to compensate for the early or late pulse, thus keeping the two clocks phase locked. If the frequencies of the two clocks differ, a succession of either "early" or "late" signals will be produced, a counter 24 will count either up or down until, at a predetermined count, an output is initiated to advance or retard stepping motor 28 one step. The motor 28 actuates potentiometer 30 to change the value of the control signal on 18 to reduce the frequency difference.
申请公布号 US3487407(A) 申请公布日期 1969.12.30
申请号 USD3487407 申请日期 1968.12.20
申请人 SIERRA RESEARCH CORP. 发明人 WILLIAM T. LENNON JR.;FREDERICK G. REINAGEL
分类号 H03J7/02;G01S11/08;G04G7/02;H03L7/06;H03L7/181;H04L7/033;(IPC1-7):G01S9/02 主分类号 H03J7/02
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