| 摘要 |
1,196,900. Control of several A.C. motors. BELOIT CORP. 8 May, 1969 [21 May, 1968], No. 23594/69. Heading H2J. The various sections of a paper-making machine are each driven by a synchronous motor associated with a source of direct-current and a plurality of inverters. A plurality of frequency converters are connected to a variable frequency source and each apply a control signal to the inverters so that each motor runs at a speed determined by the frequency of its respective converter. For each motor 48, a mains-connected rectifier 33 delivers D.C. pulses to a filter circuit 39 which develops a constant amplitude voltage across lines 40, 41, which are connected through an inverter commutation circuit 42 to an inverter bridge 43. The latter provides a three-phase voltage at a desired frequency on lines 44, 45, 46. Adjustment of source 47 changes the frequency of the inverter 43. The rectifier 33 delivers a voltage whose amplitude is proportional to the motor frequency, and, for this purpose, a feedback loop comprises a direct-current regulator 49 connected to the circuits 39, 47. The output of the regulator 49 is applied to a phase control circuit 51 which regulates the firing angle of controlled rectifiers within the unit 33. For regenerative operation of the motor, reverse current is sensed by regulator 53 associated with a phase control circuit 54 for controlled rectifiers within regenerator circuit 52. This allows current-flow from the lines 40, 41, to the lines 34, 35, 36. Each source 47 is associated with a master oscillator 55 connected to circuit 57a which allows motor 48a to run up from standstill to operating speed whilst maintaining synchronous operation. A divider circuit 58a is connected to a plurality of gates 59a for setting the division factor. A register 60a presets the gates 59a and is stepped in either direction by circuit 61a. Panel 62a displays the preset number. The speed of the whole machine is adjusted by the oscillator 55, whilst adjustment of one of the dividers 58a changes the speed of the respective section without altering the speeds of the other sections. Each phase of the source 34, 35, 36, is connected to the lines 37, 38, by identical circuits each comprising a diode in series with a silicon controlled rectifier shunted by individual resistors. A gate control circuit for the rectifier receives a fixed frequency signal and is connected in parallel with the diode and rectifier. A phase control circuit receives a fixed frequency signal as well as the signal from the regulator 49, Fig. 4 (not shown). The inverter bridge circuit 43 is associated with circuit 42 for rendering silicon controlled rectifiers in the bridge non-conductive at definite times. Each rectifier is in series with a diode and both are shunted by a resistor. A gate control circuit receives a constant frequency signal as well as two simultaneous signals from the source 47 whereby the voltage developed on lines 44, 45, 46, is approximately sinusoidal, Fig. 5 (not shown). The regenerator circuit 52 comprises a number of diode-controlled rectifier combinations connected between the lines 40, 41, and 34-36. When the motor regenerates, a phase control circuit for each rectifier is energized to permit return of current to the source, Fig. 7 (not shown). The commutation circuit 42 includes a diode and controlled rectifier in series between the units 39, 43, and a capacitor associated with a rectifier bridge connected to a separate D.C. source. The rectifier is back-biased by discharge of the capacitor. Fig. 8 (not shown). The direct-current regulator 49 comprises an amplifying transistor for the signal from the unit 47, a biasing network, and a pair of transistors with capacitive feedback acting as an integrator to provide a D.C. signal proportional to the input frequency, Fig. 9 (not shown). The phase-control circuits each comprise a transistor-capacitor network, the rate of charge of the capacitor is adjusted by a potentiometer to determine the instant at which an amplified high-frequency signal is applied to an output terminal, Figs. 10, 11 (not shown). The gate control circuits each comprise an input transformer associated with a bridge rectifier and an integrator connected to an AND gate receiving feed-back from the anode of the controlled rectifier. The AND gate supplies a monostable multivibrator connected to a driver stage for a power stage providing square-wave pulses to the gate of the controlled rectifier, Fig. 12 (not shown). The gate control circuit receives signals from the source 47 through a transistor network also receiving a fixed frequency signal which is amplified and clamped under the control of an OR-gate, Fig. 13 (not shown). The variable frequency oscillator 55 may coinprise a fixed frequency source connected to a counter circuit which is preset to count to a predetermined full-scale number. A group of gates are connected to the counter and are preset at a further predetermined number. An output of the counter is connected to the set input of a binary is connected to an AND gate which also receives a signal from the fixed frequency oscillator. The output of the AND gate forms a master clock signal which is supplied to the circuit 57, Fig. 14 (not shown). The circuit 57 comprises an AND gate and flipflop circuit receiving the signals from the oscillator 55, a multivibrator being connected to the set input of the flip-flop. The output of the flip-flop is connected to the AND gate through a switch, the multivibrator and switch being associated with a frequency control unit, Fig. 15 (not shown). The units 58-60 comprises a NAND gate connected to a counter circuit having a plurality of flip-flops determining the number of pulses from the gate before a pulse is produced by a multivibrator. The state of the flip-flops is determined by a shift register, Fig. 18 (not shown). With the application of every six pulses on an input terminal an output is produced on each of six output terminals of a multiphase generator for regulating the various silicon controlled rectifiers in the inverter bridge circuit. The generator comprises a counter formed of flip-flops associated with NAND gates, Fig. 19 (not shown). |
