| 摘要 |
PURPOSE:To shorten delay as compared with conventional input/output buffers by providing a data selector which switches the input signal of an output buffer and the output signal of an input buffer with a switching signal and outputs them. CONSTITUTION:The output of the NAND gate 21 of a data selector 12 is at a high level because a control terminal is at a low level, and the output of an inverter 20 is also at the high level, so the input signal of a terminal 1 is outputted even to the output of a NAND gate 23. This data selector 12 consists of three two-input NAND gates 21-23 and an inverter 20, but when the level of an input selection terminal CN is at the low level where a tri-state output buffer 10 is activated, the signal (I2) of the input terminal 1 appears at an output terminal 3 and the level of the input selection terminal CN make the tri-state output buffer 10 inactive.
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