| 摘要 |
PURPOSE:To enable a memory capacity of a test vector to be compressed by adding a simple circuit for reducing capacity of the test vector memory for suppressing a large capacity of the test vector memory accompanying increase in the test vector in the scan path test method. CONSTITUTION:A scan output terminal SOT1 of shift register circuits FA1-FAn according to the scan path test method are loop-connected through a simple logic circuit L1, thus enabling a test vector to be stored in an entire flip-flop circuit and a test vector value of a partial flip-flop circuit to be updated. Information on a modification point of a next test vector only for the test vector in a previous state may be provided in addition to the entire flip-flop circuit test vector for initial setting, thus enabling a data to be compressed. |
