| 摘要 |
PURPOSE:To improve the speed of writing data to and reading data from memory cells in a string connected to the same bit line faster. CONSTITUTION:Inverters IV11-IV1n and transistors Q11-Q1n connected in series between data input and output terminals of respective memory cells MC1-MCn and to data input/output terminals of the memory cell MC1, respectively, are provided. A first control signal line CL1 turning on and off the odd numbered transistors among transistors Q11-Q1n and a second control signal line CL2 turning on and off the even numbered transistors are provided. The memory cells MC1-MCn are made to act as shift resistors. |
