| 摘要 |
PURPOSE:To provide the jitter provision device providing jitter and a phase delay simultaneously. CONSTITUTION:This device is provided with a digital delay circuit 10 comprising an n-stage shift register 11 receiving a digital signal and an n-to-1 selector 12 receiving an output of the shift register 11 to its relevant input and allowing the n-to-1 selector 12 to selectively output a digital signal with an optional delay among digital signals delayed by the shift register 11, with a clock A signal source advancing the shift register 11, with a frequency divider 20 applying 1/N frequency division to the clock A, with an address counter 30 advanced by the frequency division output, and with a RAM 40 in which data representing a content of jitter are described, addressing the RAM data based on the description content of the counter 30 and outputting the addressed signal to the n-to-1 selector 12 as a selection signal. |
