| 摘要 |
<p>PURPOSE:To enable the micronization and the high integration of a semiconductor device by lightening the remainder behind the etching at formation of the pattern of the upper layer of a semiconductor device being constituted by two or more layers of transistor gate regions or capacitor region or their combination. CONSTITUTION:This is a layout mainly composed of an element isolating area 1, a lower-layer transistor area 2, an upper-layer transistor gate area 3, and a contact pattern area 5 to a drain area 4, and a layout wherein the end of the lower-layer transistor gate area 2 is projecting as compared with the end of the upper-layer transistor gate area 3.</p> |
