发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To control a logic circuit by a DC level decision circuit means and to automatically select an oscillation circuit having a needed oscillation characteristic by allowing the DC level deciding means to control the logic circuit during the fly-back period of a vertical synchronizing signal and automatically selecting the oscillation circuit. SOLUTION: A logic circuit 2 of a PLL circuit 2 selects an N type oscillation circuit 3 included in the PLL circuit 1 according to control data transmitted from a DC level decision circuit 8. A frequency division circuit 4 performs frequency division of a clock outputted from the oscillation circuit 3, and a phase comparator 5 performs phase comparison of a horizontal synchronizing signal with the clock frequency divided by the circuit 4. A charge pump circuit 6 charges up or discharges a phase difference component outputted from the comparator 5 to a loop filter on the next stage as a DC level. The circuit 8 decides a DC level obtained by a loop filter 7 which eliminates harmonic components or decides the dynamic characteristics of the PLL circuit 1.
申请公布号 JP2000183735(A) 申请公布日期 2000.06.30
申请号 JP19980356320 申请日期 1998.12.15
申请人 MITSUBISHI ELECTRIC CORP;MITSUBISHI DENKI SYSTEM LSI DESIGN KK 发明人 ONO NAOKI
分类号 H04N5/05;G09G3/20;G09G5/00;G09G5/18;H03L7/087;H03L7/089;H03L7/099;H03L7/10;H03L7/107;H03L7/18;H04N5/12;H04N5/46 主分类号 H04N5/05
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