发明名称 Clock synchronization backup mechanism for circuit emulation service
摘要 A clock synchronization backup mechanism is disclosed for maintaining clock synchronization during periods of degraded synchronization. The clock synchronization backup mechanism includes a jitter buffer having a fill value at a given sample time which is compared with a threshold. When the jitter buffer fill value exceeds the threshold, a non-normal condition is registered and the local clock frequency is set to a combination of a long-term frequency setting plus a threshold sensitive frequency adjustment. The clock synchronization backup mechanism is particularly useful for overcoming residual errors accumulated due to temperature change, oscillator degradation, and a variety of other system perturbations problematical for clock synchronization mechanisms known in the art.
申请公布号 US7191355(B1) 申请公布日期 2007.03.13
申请号 US20040888421 申请日期 2004.07.09
申请人 NORTEL NETWORKS LIMITED 发明人 OUELLETTE MICHEL;MARKANDU JEGANATHAN;AWEYA JAMES;MONTUNO DELFIN
分类号 G06F1/12;H04L12/28 主分类号 G06F1/12
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