| 摘要 |
A processor (100) comprises an ordinary instruction buffer (122) for storing and feeding one or more instructions fetched from an instruction cache (10), a TAR instruction buffer (123) for storing the one or more instructions fetched from the instruction cache (10) and feeding them secondarily, a selector (121) for selecting either the ordinary instruction buffer (122) or the TAR instruction buffer (123) as an instruction feeding source, and an instruction fetch control unit (102) for fetching, in case a TAR filling instruction is executed, one or more instruction specified by the TAR filling instruction, and for controlling the selector (121) to select the TAR instruction buffer (123), in case the one or more fetched instructions are repeatedly fed, thereby to feed an instruction through the selector (121) from the TAR instruction buffer (123). |
