发明名称 Phase locking on aliased frequencies
摘要 A phase-locked loop ( 200 ) includes a sampler ( 202 ), a phase detector ( 210 ), a loop filter ( 212 ), and a VCO ( 214 ). The loop achieves frequency multiplication without the need for a divider in the loop's feedback path. The VCO ( 214 ) is operated above the Nyquist rate of the sampler, causing the loop to lock on an aliased signal. Any variations in the VCO output frequency (i.e., jitter or phase noise) are fed back to the phase detector ( 210 ) 1-for-1, without attenuation normally associated with frequency dividers. Loop gain can therefore be kept high, even in loops that provide high closed loop frequency multiplication. According to one variation, a harmonic generator ( 540 ) is placed between the VCO and the sampler, thus causing the loop to lock on harmonics of the VCO frequency. Open loop gain and precision are thus further improved.
申请公布号 US7345549(B2) 申请公布日期 2008.03.18
申请号 US20060364534 申请日期 2006.02.28
申请人 TERADYNE, INC. 发明人 XU FANG
分类号 H03L7/085 主分类号 H03L7/085
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