PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS

摘要

Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit.