| 摘要 |
PROBLEM TO BE SOLVED: To reduce an error at the time of timing validation of a semiconductor device equipped with a transfer line connecting between chips.SOLUTION: A processor 2 selects a transfer delay corresponding to a shape of a transfer line 8 between a chip 6 and a chip 7 included in a semiconductor device 5 to be analyzed, and a resistance value, inductance, and capacitive value of the transfer line 8, out of a plurality of transfer delays based on a resistance value, inductance and capacitive value of the transfer line for each shape of the transfer line between semiconductor chips, stored in a memory part 3. Further, the processor 2 calculates an internal delay of the chip 6 and the chip 7 respectively, and based on the internal delay and the selected transfer delay, performs timing analysis of the semiconductor device 5.SELECTED DRAWING: Figure 1 |
