| 摘要 |
In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving +E,ovs CAS+EE signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit [(1 20)] (120) sets a cell plate voltage of a memory cell [(1a)] (1) approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data "1" can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving +E,ovs WE+EE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit [(201)](210). The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit. |
