Semiconductor memory device with parallel output gating.

摘要

A semiconductor memory device, comprising N memory cell arrays (11,12,13,14) each of which includes a plurality of memory cells, is arranged to enable the use of the said semiconductor memory device in either the "one-bit-per-word sequential output" form, through a single output gate (5), or the "N-bits-per-word, parallel output" form, through N output gates (31,32,33,34).