发明名称 ARITHMETIC DEVICE
摘要 PURPOSE:To accelerate the arithmetic speed, by providing plural arithmetic circuits to give operations to the prescribed two of the data read out of plural storage means. CONSTITUTION:The real number parts of multiplicand and multiplier are stored in memories 21 and 22 respectively; and the imaginary number parts of multiplicand and multiplier are stored in memories 23 and 24 respectively. Operators 31 and 32 can perform at lest additions and subtractions, and registers 33 and 34 hold the output of the operator 31 respectively. A selector 25 selects the output of the memory 21 or 22 and delivers it to a multipliers 29. A selector 26 selects the output of the memory 22 or 24 and delivers it to the multiplier 29. A selector 27 selects the output of the memory 21 or 23 and delivers it to a multiplier 30. Then a selector 28 selects the output of the memory 22 or 24 and delivers it to the multiplier 30 respectively.
申请公布号 JPS58207177(A) 申请公布日期 1983.12.02
申请号 JP19820090610 申请日期 1982.05.28
申请人 NIPPON DENKI KK 发明人 KAWAKAMI YUUICHI
分类号 G06F7/00;G06F7/48;G06F17/10 主分类号 G06F7/00
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