| 摘要 |
A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a first potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode. the first portion between said second region and said third region and a write transistor with channel length measured by the separation between said third region and said fifth region, and a storage junction formed between said fifth region and said first region. By varying the voltage on the third region during the driving of the word line to either a positive or negative voltage, the charge on the first electrode is varied thereby varying the threshold voltage of the read transistor as seen by the word line. A plurality of memory cells such as described can be used to form an array and by varying either the capacitive coupling between the word line or third region and the first electrode in a selected memory cell or, alternatively, by varying the voltage applied to the third region during the writing on said first electrode of stored charge, this particular cell can be used as a reference cell during the read operation.
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