| 摘要 |
PURPOSE:To simplify an interface between an LSI chip for substituting the functions of a CPU and a chip for substituting peripheral functions in the case of emulating a microcomputer by both the chips. CONSTITUTION:The value of a priority flag (P2i, P1i or P0i) 30 corresponding to an interruption request selected as the result of multiple interruption control is outputted to a data bus 17 by an output buffer 23 synchronously with a vector aknowledge signal 19 and address information stored in a vector ROM 22 is also simultaneously outputted to the data bus 17. Priority information and address information on the data bus are transmitted to a CPU 10 through the data bus 17. The CPU 10 stores only the priority information out of the priority information and the address information on the data bus 17 in a priority order status flag 11. |
