发明名称 FAULT ANALYZER
摘要 PURPOSE:To accurately show a change in the internal state of an ASIC necessary for the analysis of a failure to the outside of the ASIC without almost exerting influence upon the number of pins and the number of gates and missing the change. CONSTITUTION:An MPU 22 accesses the reading of the ASIC 21 and reads out information S3 to S5 necessary for the failure analysis of the ASIC 21 through an MPU bus S6. An wait signal S9 for extending the reading cycle of the MPU 22 is controlled by an wait control signal S14, and at the time of starting the reading access from the MPU 22 to the ASIC 21, an wait signal S9 is outputted to extend the reading cycle for an optional time. When the inside information of the ASTC 21 is outputted to the bus S6, a bus busy signal indicating the using of the bus S6 is outputted from the MPU 22 to an I/O 23.
申请公布号 JPH0659926(A) 申请公布日期 1994.03.04
申请号 JP19920208849 申请日期 1992.08.05
申请人 TOSHIBA CORP 发明人 AZEZAKI TSUTOMU
分类号 G06F11/22 主分类号 G06F11/22
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