| 摘要 |
PURPOSE:To provide the branchmetric arithmetic circuit which can be reduced in circuit scale by decreasing the number of branchmetric bits. CONSTITUTION:This circuit is the branchmetric arithmetic circuit of a trellis decoding circuit which decodes nonencoded bits by using encoded bits after the Viterbi decoding of a Viterbi decoding part on the basis of a reception symbol obtained by demodulating data, trellis-encoded and modulated on a transmission side, decoded on a reception side and then making a soft decision, and is equipped with an amplitude limiting means 11 which limits the amplitude of the received symbol obtained by making the soft decision and a Euclidean distance arithmetic means 13 which calculates the square of a Euclidean distance as to the data after the amplitude limitation by the amplitude limiting means 11 as the branchmetric of Viterbi decoding. |
