| 摘要 |
PURPOSE: To provide a data receiving circuit with which the phases of a clock signal and received data can be matched only with simple hardware configuration. CONSTITUTION: A received signal 23 is latched by a flip flop 33 synchronously with a clock signal 12 and latched by a flip flop 31 synchronously with an inverted clock signal 12A, and those latched data are further latched by a flip flop 32 synchronously with the clock signal 12. On the other hand, a received clock generating circuit 22 generates a received clock 24 synchronized with the received signal 23. A phase comparator circuit 36 detects phase difference between the received clock 24 and the clock signal 12 and corresponding to that phase difference, the switching of a switching circuit 34 is controlled. When this detected phase difference is larger than a reference value, the switching circuit 34 selects latch data D1 of the flip flop 33 but when the phase difference is smaller, latch, data D2 of the flip flop 32 are selected and defined as received data 14. |
