发明名称 CLOCK CONTROL SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To provide a clock control system for appropriately controlling whether or not a clock signal is to be supplied to a processor corresponding to the operating state of a device. SOLUTION: A device 1 for periodically accessing a system memory outputs a signal under Device operation showing a state under operating and a Device Request signal for requesting operation start to a device state monitoring circuit 3. On the other hand, the device state monitoring circuit 3 asserts an Enable signal during the operation of the device or asserts a Disable signal in the other case. When Stop Grant is asserted, a clock control circuit 5 asserts only STOPCLK for stopping only the internal clock of the processor and when the Stop Clock is asserted, PCLKSTP is asserted for stopping this STOPCLK and an external clock.</p>
申请公布号 JP2000357023(A) 申请公布日期 2000.12.26
申请号 JP19990169744 申请日期 1999.06.16
申请人 TOSHIBA CORP 发明人 TAKAMIYA TAKESHI
分类号 G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/04
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