发明名称 POWER REDUCTION MEMORY ELEMENT BY WAY OF BANK OPERATION CONTROL
摘要 PURPOSE: A power reduction memory element by way of a bank operation control is provided to decrease the power consumption by preventing non-selected banks from being activated. CONSTITUTION: A power reduction memory element has a PX(the boosting signal) free decoder. The PX free decoder is provided with a signal input unit(40) and a power application unit(30). The signal input unit(40) generates a bank selection signal for selecting banks in response to the low address signal(AX01), the enable signal, the NRE signal and the column address signal. The power application unit(30) generates a high voltage in response to the output signal of the signal input unit(40). The signal input unit(40) connects the first switching element receiving the column address signal at the gate terminal thereof to the earth terminal of the signal input unit(40), and connects the second switching element receiving the column address signal at the gate terminal thereof to the power supply terminal of the signal input unit(40), thereby controlling the operation of the power application unit(30). In this way, the plurality of banks arranged at the left and the right of the low decoder are distinguished from each other, and selectively activated.
申请公布号 KR100332469(B1) 申请公布日期 2002.04.01
申请号 KR19980019782 申请日期 1998.05.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 WON, JANG GYU
分类号 H01L27/10;(IPC1-7):H01L27/10 主分类号 H01L27/10
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