| 摘要 |
The channel region ( 11 ) and the source-drain regions ( 9, 10 ) are arranged vertically at a sidewall of a dielectric trench filling ( 4 ). On the opposite side, the semiconductor material is bounded by the gate dielectric ( 18 ) and the gate electrode ( 16 ), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.
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