发明名称 SYSTEM AND METHOD FOR PLL (PHASE-LOCKED LOOP) LEAK COMPENSATION
摘要 PROBLEM TO BE SOLVED: To provide a PLL system and its method for compensating current leak which may include gate-leak current attributable to a gate capacitor. SOLUTION: A compensation current is supplied to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leak, and accordingly, reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter, and then provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without using the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006345512(A) 申请公布日期 2006.12.21
申请号 JP20060145839 申请日期 2006.05.25
申请人 TOSHIBA CORP 发明人 TAKASE SATORU
分类号 H03L7/093;H03L7/10 主分类号 H03L7/093
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