| 摘要 |
A delay locked loop is provided to control current flowing in a regulator by using a selection signal determining the delay amount of a delay line, thereby improving current consumption efficiency. In a delay locked loop of a semiconductor memory device, a plurality of delay cells is connected in series and delays an inputted clock as much as a fixed phase difference in response to each selection signal. A regulator(420) senses a reference voltage and the voltage level of an output node, and provides current to the delay cells through the output node, and changes the current intensity of the output node according to each selection signal. A selection circuit(440) provides each selection signal to the delay cells and the regulator in response to a control signal.
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