| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a new configuration which is capable of suitably suppressing passing between information write to a memory and information read from the memory. <P>SOLUTION: The occurrence of passing is predicted by a count value of a horizontal synchronizing signal IHS for write at the time of the start of data read from a frame memory. When start and end positions of write are on respective reference lines, passing will occur in the case that the count value of the signal IHS is within a range between upper and lower limit lines. Comparing parts (1)509 and (2) 510 and an OR element 511 determine whether or not an IHS count value outputted from a count value storage part 502 and an IHS count value outputted from an adder 503 allowing for offset are included within a range between corrected upper and lower limit lines corrected by input ACT difference line information indicative of deviation from the reference line of a write start line and input offset line information indicative of deviation from the reference line of a write end line. <P>COPYRIGHT: (C)2007,JPO&INPIT |
