| 摘要 |
When the core 10 is powered down the output buffer 16 selectively outputs either (a) a retained and latched present logical state, which may be a high, a low, or a high-impedance state, or (b) an inactive logic state such as a high-impedance state. Power down of the core is sensed by circuit 24, which selectively asserts RTO to open the switches SW2,SW3 or asserts SNS to close SW1 under control of a mode bit stored in control latch 24. The signal RET can be asserted by a central controller, or generated locally following core power-up, to ensure output logic state retention when the core is powered down. The signal RET can be tied low if it is known at design stage that state retention will not be required. The buffer 16 may drive a signal outside the IC or may drive other domains within the IC. The buffer control circuit 22 may control several buffers. A central controller is not required to coordinate latching. |
