SYSTEM AND METHOD FOR BUS BANDWIDTH MANAGEMENT IN A SYSTEM ON A CHIP

摘要

Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time to identify valid bits uniquely associated with transaction requests issued by a master processing engine. The method continues to monitor the bus over the window to identify completed transactions. A latency value is calculated by subtracting a target latency from an actual latency for each completed transaction. The latency value is aggregated in a counter. At the conclusion of the window, if the aggregated latency value is positive, the method may conclude that the average latency per transaction over the window exceeded the target latency per transaction and that the bandwidth allocated to the engine should be increased.

主权项

1. A method for managing bus bandwidth allocation in a system on a chip (“SoC”), the method comprising:
monitoring over a first measurement window a bus to identify valid bits uniquely associated with transaction requests issued by a master processing engine; for each identified valid bit, incrementing each of a Total Valid Transaction Counter (“TVTC”) and a Running Valid Transaction Counter (“RVTC”) by one; monitoring over the first measurement window the bus to identify completed transactions; for each identified completed transaction, decrementing the RVTC and adding a latency value to a Total Latency Aggregator (“TLA”) value, wherein the latency value is calculated by subtracting a target latency from an actual latency for a given completed transaction; at the conclusion of the first measurement window, determining the sign of the TLA value; increasing a bandwidth allocation to the master processing engine if the TLA value is positive; and decreasing a bandwidth allocation to the master processing engine if the TLA value is negative.