HARDWARE ACCELERATOR AND CHIP

摘要

Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an nth period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

主权项

1. A hardware accelerator, comprising: an interface circuit and an accelerator core coupled to the interface circuit, wherein the interface circuit comprises: an input/output (I/O) interface, a queue manager, and a scheduling controller; wherein
the I/O interface is configured to receive a first task request, wherein the first task request carries identifier information used to indicate a communications standard to which the first task request belongs, and a priority of the first task request; the queue manager comprises: a decoding circuit and at least two channel groups, wherein the at least two channel groups are respectively corresponding to at least two preset communications standards, each channel group is corresponding to one communications standard, any one of the channel groups comprises at least one first in first out (FIFO) queue, and the at least one FIFO queue is respectively corresponding to at least one preset priority; and the decoding circuit is configured to perform decoding on the first task request to acquire the identifier information, and configure, according to the identifier information, the first task request to be in a FIFO queue that matches the identifier information; the scheduling controller is configured to determine, from the at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an nth period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm, wherein the nth period is any period in which the scheduling controller performs periodic scheduling on a task request in the at least two channel groups, and n is a natural number; and the accelerator core is configured to respond to the at least one scheduled second task request.