| 发明名称 |
CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM |
| 摘要 |
A cache memory system has a first cache memory comprising one or more level, to store data corresponding to addresses, a second cache memory comprising a plurality of non-volatile memory cells, which has higher speed capability than a main memory, has a larger capacity than the first cache memory and stores data corresponding to addresses, and a first storage to store address conversion information from a virtual address issued by a processor to a physical address and to store flag information indicating whether data is stored in the second cache memory by a page having a larger data amount than a cache line, the first cache memory being accessed by the cache line. |
| 申请公布号 |
US2016196210(A1) |
申请公布日期 |
2016.07.07 |
| 申请号 |
US201615069409 |
申请日期 |
2016.03.14 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
NOGUCHI Hiroki;FUJITA Shinobu |
| 分类号 |
G06F12/08;G06F12/10 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A cache memory system comprising:
a first cache memory comprising one or more level, to store data corresponding to addresses; a second cache memory comprising a plurality of non-volatile memory cells, which has higher speed capability than a main memory, has a larger capacity than the first cache memory and stores data corresponding to addresses; and a first storage to store address conversion Information from a virtual address issued by a processor to a physical address and to store flag information indicating whether data is stored in the second cache memory by a page having a larger data amount than a cache line, the first cache memory being accessed by the cache line. |
| 地址 |
Tokyo JP |
