| 摘要 |
1,053,147. Electronic calculating apparatus. CONTROL DATA CORPORATION. June 3, 1964 [June 4, 1963], No. 22926/64. Heading G4A. Multiplication of two binary numbers is effected by notionally dividing the multiplier into two parts, simultaneously effecting a multiplication of the multiplicand by each, and subsequently adding the two partial products so obtained. To further speed up the process, the multiplier bits in each part are examined in pairs, which control the adding-in of zero, or 1 x , 2 x or 3 x the multiplicand. As shown, the multiplier is first loaded into L-2u and L-2L (most and least significant parts) via A1, and the multiplicand into X-1. The apparatus uses two " adding pyramids " described in Specification 1,053,146, and shift units 16, 16<1> which effectively enter numbers into the pyramids at one higher binary order (this multiplying by two). Thus by opening gates 12 and 14 A-1 can deliver 3 x multiplicand to X2. Translators A-1, Q-1 now sense the two lower order bits in both L-2u and L-2L to control the delivery to the pyramids via gates 24 of the appropriate multiple of the multiplicand, where it is added to the contents of the accumulator sent via gates 30, 30<1>, and shift pulses shift the two lowest bits of the partial product into L-2u, L-2L which are arranged to form single shift registers with the accumulators. Thus the next two bits of each half of the multiplier are ready for translation. Finally the partial products now shifted into L-2u, L-2L are supplied (appropriately aligned) to the adding pyramids to produce the final (doublelength) product which is sent to the accumulators. |
