发明名称
摘要 PURPOSE:To receive signals without fail by a method wherein, when vertical CCD registers are respectively arranged between multiple rows of photoelectric conversion elements to be connected respectively to multiple stepped horizontal CCD registers through the intermediary of transistors controlling conduction and non-conduction, a potential wall is provided below a gate wiring of transistor putting aside on a gate region. CONSTITUTION:Vertical CCD registers 2 are respectively arranged between multiple rows of photoelectric conversion elements 1 comprising light emitting diodes and then one side ends of the registers 2 are connected to multiple stepped horizontal CCD registers 3'-1-3'-n through the intermediary of gate wirings 6-1-6-n comprising transistors 5-1-5-n while charge is transferred from the final ends to MOS type source follower circuit 4-1-4-n as output steps. In such a constitution, an ion implanted layer 7 as a potential wall is preliminarily formed putting aside on a gate region through the intermediary of a gate oxide film 10 below the gate electrode 6 of each transistor while the electrode 6-E may be impressed with voltage to transfer charge to the circuit 4 without fail.
申请公布号 JPH0618266(B2) 申请公布日期 1994.03.09
申请号 JP19840248116 申请日期 1984.11.26
申请人 HITACHI LTD 发明人 KOIKE NORIO;NAKAI MASAAKI;ONO HIDEYUKI;OOBA SHINYA;ANDO HARUHISA;OZAKI TOSHIBUMI
分类号 H01L27/14;H01L27/146;H01L27/148;H04N5/335;H04N5/341;H04N5/3728;(IPC1-7):H01L27/148 主分类号 H01L27/14
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