| 摘要 |
1,158,927. Radar. HOLLANDSE SIGNAALAPPARATEN N.V. 12 Sept., 1966 [14 Sept., 1965], No. 40708/66. Heading H4D. The Specification describes a pulse radar target tracking system whereby a target selected from a P.P.I. display 12, Fig. 1, can be tracked by means of a tracking window C 1 , C 2 , C 3 , C 4 , Fig. 2, based on an assumed target position D v and any errors detected between the assumed target position and that evident from the position of the echoes E 1 -E 12 , used to correct the position of the tracking window. The video signals on line 10 are passed through a gating circuit 11 having an azimuth gate control 16 and a range gate control 18. The assumed target position is stored in a computer 19, which generates the azimuth and range gating signals and is also fed with the output of the gating circuit to determine said tracking error. Digital selecting and discriminating means 20 and 21 aid the computer in its determination. Operation of azimuth circuits, Figs. 3, 4.-In Fig. 3, everything below the dotted line is included in the digital selecting and discriminating means of Fig. 1. A converter 9, Fig. 1 coupled to the Aerial shaft generates a pulse each 10<SP>-3</SP> radian of azimuth rotation and these pulses are fed to the computer 19, whence at the beginning of each of eight 45 degree azimuth sectors, the difference between the Aerial azimuth angle #.ant, Fig. 2 and the angle of the beginning of the window is determined, and when this difference # is less than 45‹ degrees the computer produces a signal on line 41 which sets bi-stable circuit 33 to open gate 30, such that a first digital counter 22 can begin to count the azimuth pulses. Said difference angle # is set in counter 22 as a negative number, such that when the azimuth pulses counted are such that the aerial starts to sweep the window-i.e. # ant = B v - ½ where B v = assumed azimuth of target, a = half angular width of window -, the total count of counter 22 is zero i.e. # = 0. A signal on line 42 is then produced which opens the azimuth gate 16 and also opens a gate 31 via a bi-stable circuit 34, such that a second digital counter 24 can start counting synch pulses s from the transmitter, and produce a pulse from decoder 23 when a number of synch pulses has been counted proportional to the width 2α of the window. This pulse is used to close the azimuth gate and stop the synch pulse count. To determine the actual azimuth of the target the video is fed to a twenty stage shift register 25 which is shifted by each synch pulse and registers a 1 when an echo is received, and an 0 when it is not. The first ten stages are coupled to a first summing circuit 26 and the second ten stages are coupled to a second summing circuit 27. The output of the second summing circuit is subtracted from that of the first summing circuit in a difference amplifier 28. Thus, if Fig. 4a represents the twenty four successive returns received during the window, and E 1 -E 12 represent the twelve successive echoes received from a target to the left of its assumed position, then the output of the difference amplifier is shown at VD 1 in Fig. 4b. The output increases until the first ten echoes set the first ten stages of the register into 1 states. The next (last) three echoes cause the first three stages of the second ten stages of the register to be set to the 1 state resulting in the fall by unit increments of the difference amplifier output. No further echoes being received, the-thirteen 1 states shift through the register, causing the fall by two unit increments of the amplifier output. When the output falls to zero, a signal is fed via gate 32 to the computer 19. It is seen that the true azimuth of the target is given by subtracting an angle equivalent to ten synch pulse from the azimuth angle prevailing at the moment the signal is fed to the computer. The computer is thus able to determine the azimuth error of the window and correct. If less than eight or more than sixteen echoes are received indicating interference or a return from clutter, a third digital counter 37, counting the echoes disables gate 32 and sends an "ignore" signal to the computer. Operation of range circuits, Figs. 5, 6.-At a time prior to the sweeping of the window a number in computer 19 representing the assumed target range plus half the range gate is fed to register 47. On the time scale of Fig. 6 this is represented by time t 2 , the assumed target echo occurring at t 1 and the range gate lasting from t 0 to t 2 , equivalent to 1000 m. Prior to the synch pulse S of the first return in the window the number in register 47 is transferred to first digital counter 48. A pulse generator 51 produces range pulses at a rate of 4.79 Mc/s representing range increments of 31.25 m. These are fed to counter 48, 6.6 Á sec. before the synch pulse by means of a correcting pulse Sc opening gate 52. The counted pulses subtract from the number in the counter such that the count therein falls to zero at time t 0 . A pulse is then produced opening the range gate. When a negative count of thirty two pulses is reached, represent 1000 m. at t 2 , a second pulse is produced closing the range gate. The counter also produces a switching pulse at time t 3 . A gated echo pulse opens gate 53 via gate 54 and bi-stable circuit 56, such that the range pulses are counted by counter 50. The switching pulse at time t 3 closes gate 53 via gate 62, gate 65 and bi-stable 56 such that the count in counter 50 indicates the number of range pulses occurring between the echo signal and time t 3 . If the echo signal is in the centre of the range gate, this count should be thirty-two, and any departure from this represents a range gate error and can be used by the computer for tracking purposes. In practice, however, the average error over eight returns is used and the output of the fourth stage of the counter 50 is thus fed to the computer. Gate 54 shuts after eight successive echo returns. If two echoes are received in the range gate, counter 50 is stopped at a count of thirty two. A counter 58 counts the number of echo pulses and on detecting more than one causes a pulse from counter 49 which is produced thereby at a count of thirty two, to close gate 53 via gate 61, gate 66 and circuit 56. If three successive such double returns are detected by counter 68 an "unreliable" signal is fed to computer 19. |
