发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To quicken phase synchronization locking by keeping a damping constant to be a prescribed value even against the changeover of an input signal frequency with respect to the phase locked loop circuit used for clock recovery or the like. CONSTITUTION:A phase of the output signal of a voltage controlled oscillator 1 and the phase of an input signal are compared by a phase comparator 2 and its output is used for a control voltage of the voltage controlled oscillator 1 via a loop filter 3. The loop filter 3 of the phase locked loop circuit is provided with 1st and 2nd voltage current converters 4, 5, a capacitor 6 charged/ discharged by the output current of the 1st voltage current converter 4, and a resistor 7 receiving an output current of the 2nd voltage current converter 5, a ratio of a control current of the input stage of a current multiplier section being components of the 1st and 2nd voltage current converters 4, 5 to a control current of an output stage is selected corresponding to the changeover of the input signal frequency to select a conversion coefficient without changing a damping constant.
申请公布号 JPH06140927(A) 申请公布日期 1994.05.20
申请号 JP19920289773 申请日期 1992.10.28
申请人 FUJITSU LTD 发明人 SHIMODA KANEYASU
分类号 H03L7/093;H03L7/10;H03L7/107 主分类号 H03L7/093
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