| 摘要 |
PURPOSE:To form a digital timing recovery circuit without requiring a multiplier. CONSTITUTION:A synchronizing device 12 receives a signal. A timing recovery circuit 20 controls the sampling ratio. The in-phase and quadrature phase signal outputted through a Nyquist filter 16 passes through a nonlinear arithmetic circuit 22 and passes a Bycad structure filter 28 having the center of a passband in the symbol ratio of the accepted signal. The quadrature output signal of the biquartic structure filter 28 is generated by a signal generator 38 as a function of the sampling ratio. With the correction with the internal signal, a frequency error signal is generated. A DPLL circuit 30 accepts a frequency error signal and generates a control signal to control the sampling ratio of an A/D converter. The DPLL circuit 30 adjusts the sampling ratio till the biquartic structure filter output is phase-synthesized with the output signal of the internal signal generator 38. |
