| 摘要 |
PURPOSE:To let signals of good responsiveness and less chattering phenomena be outputted by connecting two sets of chattering preventing circuits to which timing pulses of different phases are applied respectively parallel and series to a switch circuit. CONSTITUTION:When a switch 1 is closed for the purpose of time correction or other, the first chattering preventing circuit 2 formed by NOR gate 2a and inverter 2b which are parallel connected and to which timing clock phic11 is applied causes the switch output P to become high level irrespective of chattering of the switch 1 when the clock phic11 is low level. On the other hand, the second chattering preventing circuit 3 which is constituted by a D type FF and is series-connected with the switch 1 is applied with such timing clock phic12 of a different phase that reads in the signal P when the clock phic11 is low level. When the switch 1 is closed, the signal P is read into the circuit 3 only when the signal P from the circuit 2 is high level even if chattering occurs, thus the control signal having no effect of chattering is outputted with good responsiveness. |
