High speed address transition detector circuit for dynamic read/write memory

摘要

A transition of an address input of a memory device is detected in a CMOS circuit having a pair of AND gates Or'ed together. One AND gate receives the input bit and a delayed complement of this bit. The other AND gate receives the complement of the input bit and a delayed version of the true bit. The delays are RC circuits with time constants longer than the transition times. The output of the gates uses a pull-up device to restore a zero level after each transition is indicated. A number of these transition detectors may be OR'ed together to monitor all of the address bits of a memory device.