| 摘要 |
PURPOSE:To prevent simultaneous access of a memory by extracting plural input signals in time division when the plural input signals are applied as if plural memory write request signals were generated at the same time. CONSTITUTION:The 1st flip-flop groups FF1-FF3 storing respectively plural input signals 8a-8c, the 2nd flip-flop groups FF4-FF6 connected mutually by a gate circuit 10 as a shift register and forming a time division signal and a processing circuit 7 generating a processing end signal are provided. When plural input signals exist just like the simultaneous presence of plural memory write request signals, the plural input signals are extracted sequentially in response to the output state of the FF4-FF6 and converted into a singular memory write request signal. Thus, the simultaneous access of the memory is prevented.
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