发明名称 Delay time calculating method by delay equivalent circuit
摘要 There is provided a delay time calculation method, which simplifies a delay time calculation of an interconnection wiring which includes inductance, within a semiconductor integrated circuit, so that the calculation can be executed by use of the delay time calculating CAD tool used in the prior art. A delay time of a wire model consisting of three components of inductance (L), capacitance (C) and resistance (R), is obtained by an analysis equation and an approximation calculation, and a circuit consisting of a second resistance (R') and a second capacitance (C') and having a delay time equivalent to the delay time obtained is imaginarily constructed. The delay time is calculated by using the value of the second resistance (R') and the value of the second capacitance (C') obtained in this method.
申请公布号 US2002112218(A1) 申请公布日期 2002.08.15
申请号 US20010845772 申请日期 2001.05.02
申请人 NAKAMURA KAZUYUKI;LENOIR PATRICK 发明人 NAKAMURA KAZUYUKI;LENOIR PATRICK
分类号 G01R31/28;G06F17/50;H01L21/82;H01L29/00;(IPC1-7):G06F17/50 主分类号 G01R31/28
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